VLSI circuit complexity has made testing difficult and more expensive. Increasing the testability of a design becomes one of the important issues in the design cycle of VLSI circuits because it helps to achieve the high test quality and to reduce test development and test application costs. In the past, it was possible to add design-for-testability (DFT) circuits manually after logic synthesis. However, current needs for a shorter time to market make this approach an unaffordable design bottleneck. Ignoring DFT during the design cycle affects product quality and introduces schedule delays. Therefore, most industrial digital designs use automated synthesis, and DFT may be achieved by incorporating test and synthesis into a single methodology that is as automated as possible. Indeed, considering testability during the design synthesis, as opposed to traditional approaches of making back-end modification after an implementation has been generated, may significantly reduce design time.
Programmable platform architectures for VLSI chip design provide a set of resources (IP) to help facilitate the different chip designs that are applied to the platform. Typically this involves the integration of complex IP (intellectual property), which is challenging from a point view of the manufacturing test and test insertion. When such complex IP is used, there is often a very significant effort and schedule involved with the insertion, validation and test bringup of such IP in the manufacturing environment. In addition, in a platform environment it is often the case that not all of the platform resources are used. In such cases, these unused resources do not require testing and must be rendered inert relative to the rest of the system. If the unused resource cannot be made inert, then it must be instantiated for at least test purposes. However, this may complicate the chip validation problem and reduce effective yield.
In order to solve the foregoing problems, in the past DFT circuits (testing structures) were later inserted at a netlist level. However, this method may add months to a chip's schedule. Moreover, it is possible to discover that a design cannot be tested within the bounds of chip resources because of the limitations on available I/Os, power capacity, routing resources, timing closure, thermal issues, manufacturing tester limitations (such as pin location restrictions, max scan chains), and the like. Furthermore, this method may inject undetectable errors, and/or require significant and expensive late in the game design changes, which may literally set the design back to square 1 (this iteration loop may repeat itself over and over again).
Therefore, it would be advantageous to provide a method and apparatus to automatically configure where required, and/or insert where needed, chip resources for manufacturing tests in a way that is of minimal impact to the customer while facilitating the creation of manufacturing tests that are as sophisticated as they need to be.